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[SCMDDS数字信号发生器

Description: DDS数字信号发生器,采用AD9835DDS 专用芯片 输出范围1K--10MHZ 采用X25045作看门狗及数据存储器,用于设置各项参数的存储 内含电路图, 源程序 及一些相关资料-DDS digital signal generator, using AD9835DDS ASIC output range 1K-- Knoxville watchdog for the use of X25045 and data memory, used to set various parameters of storage containing circuit, the source and related information
Platform: | Size: 2220032 | Author: 董庆 | Hits:

[Communication-MobileDDS+PLL

Description: 基于FPGA的新的DDS+PLL时钟发生器-FPGA-based new DDS PLL clock generator
Platform: | Size: 145408 | Author: 李敏 | Hits:

[SCMDDS

Description: 基于fpga,采用quartus2的DDS信号发生器,采用高速DAC908为数模芯片,并可通过51单片机送入调制信号进行FM调制-Based on the fpga, the use of the DDS signal generator quartus2 using DAC908 number of high-speed chip module, and passed into 51 single-chip FM modulation signal modulation
Platform: | Size: 2745344 | Author: 张新 | Hits:

[SCMFPGA--DDS-PhaseMeasure

Description: Verilog实现的DDS正弦信号发生器和测频测相模块,DDS模块可产生两路频率和相位差均可预置调整的值正弦波,频率范围为20Hz-5MHz,相位范围为0°-359°,测量的数据通过引脚传输给单片机,单片机进行计算和显示。-Verilog realize the DDS sine wave signal generator and frequency measurement module test phase, DDS module can generate both frequency and phase difference can be preset to adjust the value of sine wave, frequency range of 20Hz-5MHz, phase range of 0 °-359 ° , measurement data and transmit them to the single-chip pin, single-chip microcomputer to calculate and display.
Platform: | Size: 1371136 | Author: haoren | Hits:

[SCMDDS

Description: 基于DDS技术的数控信号发生器的设计程序,也有两种语言。-Based on DDS technology of CNC signal generator of the design process, there are two languages.
Platform: | Size: 10240 | Author: 康天照 | Hits:

[OtherDDS

Description: 基于DDS技术构建信号发生器.pdf,版权归原作者所有,谨供学习,不得用作商业用途。-Based on DDS technology to build signal generator. Pdf, belongs to original author, would like for learning, not to be used for commercial purposes.
Platform: | Size: 232448 | Author: 滕飞 | Hits:

[SCMDDS

Description: 基于AD9851的DDS信号发生器的c语言编程-AD9851 Based on the DDS signal generator of c language programming
Platform: | Size: 6144 | Author: tan | Hits:

[matlabDDS

Description: 用MATLAB中的SIMULINK工具实现DDS的仿真模型,不过这里的控制字是常量-SIMULINK with MATLAB tools in DDS realize the simulation model, but here the control word is a constant
Platform: | Size: 55296 | Author: zhangli | Hits:

[VHDL-FPGA-VerilogDDs

Description: 这是我的毕业设计,是用VHDL编程的直接扩频发生器。-This is my graduation project is the use of VHDL programming direct spread-spectrum generator.
Platform: | Size: 459776 | Author: shengm1 | Hits:

[VHDL-FPGA-Verilogdds

Description: 基于CYCLONE II的程序,DDS原理的函数信号发生器.采用查表法实现.各位可以参考.-CYCLONE II based on the procedure, DDS Function Generator principle. Realize the use of look-up table method. Members may refer to.
Platform: | Size: 231424 | Author: Yin | Hits:

[Other Embeded programDDS

Description: 基于DDS的数字移相正弦信号发生器设计,EDA技术在全国大学生电子设计竞赛中的应用-DDS-based digital phase-shifting sinusoidal signal generator design, EDA Technology in the National Undergraduate Electronic Design Contest Application
Platform: | Size: 222208 | Author: Alex | Hits:

[Other Embeded programdds_drive.c

Description: DDS发生器NIOS .c文件,在NIOSII中可以配合Verilog代码生成的自定义外设产生DDS信号-DDS generator NIOS. C files, NIOSII can be in Verilog code generation with custom peripherals DDS generated signal
Platform: | Size: 4096 | Author: 白天 | Hits:

[WaveletDDS

Description: 利用EDA技术和FPGA在UP3开发板上实现直接数字频率综合器的设计。 实验中加入了相位控制字PWORD,用以控制相位偏移量的前四位,将相位偏移量加到ROM地址总线 上,从而引起从ROM中取得的正弦信号的偏移,实现移相信号发生器的移相功能。 实验中还加入了LCD显示功能,通过LCD显示模块器件,用LCD显示正弦信号的频率,所显示的频 率也是由频率字控制的。LCD的驱动原理同上次实验。-The use of EDA technology and FPGA development in the UP3 board direct digital frequency synthesizer design. Experiment by adding a phase control word PWORD, to control the phase offset of the top four will be added to the phase offset ROM address bus, thereby causing ROM obtained from the sinusoidal signal offset, shifted believe realize its phase-shifting function generator. Experiments have also joined the LCD display, LCD display module through the device, with LCD display the frequency of sinusoidal signal, as shown by the frequency of word frequency control. LCD driving principles with the previous experiment.
Platform: | Size: 1225728 | Author: Emma | Hits:

[SCMDDS

Description: 用8051控制DDS信号发生器,产生1HZ-10MHz的正弦波/三角波/方波-DDS with 8051 control signal generator, producing the 1HZ-10MHz sine/triangle/square wave
Platform: | Size: 43008 | Author: 徐小平 | Hits:

[Software EngineeringDDS

Description: 基于DDS原理的正弦信号发生器。用VERILOG语言实现,功能强大。-DDS based on the principle of sinusoidal signal generator. Using Verilog language and powerful.
Platform: | Size: 558080 | Author: 毛华站 | Hits:

[SCMDDS

Description: 利用FPGA的资源实现任意波形的产生,再若和单片机配合就能做成任意的波形发生器。-Use of FPGA resources for the realization of arbitrary waveform generation, again if and SCM can be made with the arbitrary waveform generator.
Platform: | Size: 520192 | Author: 张军 | Hits:

[Communicationdds

Description: matlab下实现的DDS发生器,可观察其发生信号的波形,频谱。 运行前请先输入 global theta theta=0 -matlab implementation of the DDS generator, may happen to observe the signal waveform, spectrum. Please enter a pre-operational global theta theta = 0
Platform: | Size: 10240 | Author: yanli | Hits:

[Software EngineeringDDS-baseddesignofthesinusoidalsignalgenerator

Description: 本设计采用AT89552单片机,辅以必要的模拟电路,实现了一个基于直接数字频率合成技术(DDS)的正弦谊号发生器。设计中采用DDS芯片AD9850产生频率1KHZ~10MHZ范围内正弦波,采用功放AD811控制输出电压幅度, 由单片机AT89S52控制调节步进频率1HZ。在此基础上,用模拟乘法器MC1496实现了正弦调制信号频率为1KHZ的模拟相度调制信号;用FPGA芯片产生二进制NRZ码,与AD9850结合实现相移键控PSK、幅移键控ASK、频移镇键FSK。-AT89552 the single-chip design, supplemented by the necessary analog circuits, based on the realization of a direct digital frequency synthesis (DDS) generator of sinusoidal No. Friends. The design of DDS chip AD9850 produced using 1KHZ ~ 10MHZ frequency range of sine wave, the AD811 control amplifier output voltage range of from single-chip AT89S52-conditioning step frequency control 1HZ. On this basis, the use of analog multiplier MC1496 has sinusoidal frequency modulation signal 1KHZ degree analog phase modulated signal generated by FPGA chip NRZ binary code, combined with the AD9850 to achieve phase shift keying PSK, ASK ASK, frequency Shift key town of FSK.
Platform: | Size: 208896 | Author: 何蓓 | Hits:

[VHDL-FPGA-Veriloggenerator.new

Description: AVR DDS Generator. It designed for AtMega16 or similar. It can generate Sinus, Saw, Square and triangle.
Platform: | Size: 232448 | Author: Martin Valensky | Hits:

[VHDL-FPGA-VerilogVerilog-dds

Description: 用Verilog实现的DDS,直接频率合成器,相位可调。-Verilog DDS generator
Platform: | Size: 1184768 | Author: fu | Hits:
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